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| Microcomputer Components 8-Bit CMOS Microcontroller C515A Data Sheet 10.97 C515A Data Sheet Revision History: Previous Version: Page Page (in previous (in current Version) Version) Current Version: 10.97 none Subjects (major changes since last revision) Edition 10.97 Published by Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstrae 73, 81541 Munchen (c) Siemens AG 1997. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you - get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered. 8-Bit CMOS Microcontroller C515A Advance Information * * * * * * * * * * Full upward compatibility with SAB 80C515A/83C515A-5 Up to 24 MHz external operating frequency - 500 ns instruction cycle at 24 MHz operation 32K byte on-chip ROM (with optional ROM protection) - alternatively up to 64K byte external program memory Up to 64K byte external data memory 256 byte on-chip RAM 1K byte on-chip RAM (XRAM) Six 8-bit parallel I/O ports One input port for analog/digital input Full duplex serial interface (USART) - 4 operating modes, fixed or variable baud rates Three 16-bit timer/counters - Timer 0 / 1 (C501 compatible) - Timer 2 for 16-bit reload, compare, or capture functions (further features are on next page) Oscillator Watchdog On-Chip Emulation Support Module Watchdog Timer XRAM 1Kx8 T0 RAM 256 x 8 Port 0 I/O Port 1 CPU USART Port 2 ROM 32 k x 8 I/O Power Saving Modes 10-Bit A / D Converter T2 T1 I/O Port 6 Port 5 Port 4 Port 3 I/O Analog / Digital Input I/O I/O MCA03239 Figure 1 C515A Functional Units Semiconductor Group 3 1997-10-01 C515A Features (cont'd): * * * * * * * * 10-bit A/D converter - 8 multiplexed analog inputs - Built-in self calibration 16-bit watchdog timer Power saving modes - Slow down mode - Idle mode (can be combined with slow down mode) - Software power down mode with wake-up capability through INT0 pin - Hardware power down mode 12 interrupt sources (7 external, 5 internal) selectable at 4 priority levels ALE switch-off capability On-chip emulation support logic (Enhanced Hooks Technology TM) P-MQFP-80-1 package Temperature Ranges: SAB-C515A TA = 0 to 70 C SAF-C515A TA = - 40 to 85 C SAH-C515A TA = - 40 to 85 C SAK-C515 TA = - 40 to 110 C (max. operating frequency: 18 MHz) The C515A is an upward compatible version of the SAB 80C515A/83C515A-5 8-bit microcontroller which additionally provides an improved 10-bit A/D converter, ALE switch-off capability, on-chip emulation support, ROM protection, and enhanced power saving mode capabilities. With a maximum external clock rate of 24 MHz it achieves a 500 ns instruction cycle time (1 s at 12 MHz). The C515A is mounted in a P-MQFP-80 package. Ordering Information Type SAB-C515A-4RM SAF-C515A-4RM Ordering Code Package Description (8-Bit CMOS microcontroller) Q67121-DXXXX P-MQFP-80-1 with mask programmable ROM (18 MHz) Q67121-DXXXX P-MQFP-80-1 with mask programmable ROM (18 MHz) ext. temp. - 40 C to 85 C SAB-C515A-4R24M Q67121-DXXXX P-MQFP-80-1 with mask programmable ROM (24 MHz) SAF-C515A-4R24M Q67121-DXXXX P-MQFP-80-1 with mask programmable ROM (24 MHz) ext. temp. - 40 C to 85 C SAB-C515A-LM SAF-C515A-LM SAB-C515A-L24M SAF-C515A-L24M Q67121-C1068 Q67121-C1069 Q67121-C1070 Q67127-C2020 P-MQFP-80-1 for external memory (18 MHz) P-MQFP-80-1 for external memory (18 MHz) ext. temp. - 40 C to 85 C P-MQFP-80-1 for external memory (24 MHz) P-MQFP-80-1 for external memory (24 MHz) ext. temp. - 40 C to 85 C Note: Versions for extended temperature ranges - 40 C to 110 C and - 40 C to 125 C (SAH-C515A and SAK-C515A) are available on request. The ordering number of ROM types (DXXXX extensions) is defined after program release (verification) of the customer. Semiconductor Group 4 1997-10-01 C515A V CC V SS XTAL1 XTAL2 Port 0 8-Bit Digit. I / O Port 1 8-Bit Digit. I / O ALE PSEN EA Port 2 8-Bit Digit. I / O C515A RESET PE / SWD HWPD Port 3 8-Bit Digit. I / O Port 4 8-Bit Digit. I / O Port 5 8-Bit Digit. I / O V AREF V AGND Port 6 8-Bit Analog / Digital Input MCL03240 Figure 2 Logic Symbol Additional Literature For further information about the C515A the following literature is available: Title C515A 8-Bit CMOS Microcontroller User's Manual C500 Microcontroller Family Architecture and Instruction Set User's Manual C500 Microcontroller Family - Pocket Guide Ordering Number B158-H7051-X-X-7600 B158-H6987-X-X-7600 B158-H6986-X-X-7600 Semiconductor Group 5 1997-10-01 C515A P5.6 P5.5 P5.4 P5.3 P5.2 P5.1 P5.0 N.C. HWPD N.C. N.C. P4.0 / ADST P4.1 P4.2 PE / SWD P4.3 P4.4 P4.5 P4.6 P4.7 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 61 40 39 62 38 63 37 64 36 65 35 66 34 67 33 68 32 69 70 31 C515A 30 71 29 72 28 73 27 74 26 75 25 76 24 77 23 78 22 79 80 21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 P5.7 P0.7 / AD7 P0.6 / AD6 P0.5 / AD5 P0.4 / AD4 P0.3 / AD3 P0.2 / AD2 P0.1 / AD1 P0.0 / AD0 N.C. N.C. EA ALE PSEN N.C. P2.7 / A15 P2.6 / A14 P2.5 / A13 P2.4 / A12 P2.3 / A11 P2.2 / A10 P2.1 / A9 P2.0 / A8 XTAL1 XTAL2 V SS V SS V CC V CC P1.0 / INT3 / CC0 P1.1 / INT4 / CC1 P1.2 / INT5 / CC2 P1.3 / INT6 / CC3 P1.4 / INT2 P1.5 / T2EX P1.6 / CLKOUT P1.7 / T2 N.C. P3.7 / RD P3.6 / WR RESET N.C. V AREF V AGND P6.7 / AIN7 P6.6 / AIN6 P6.5 / AIN5 P6.4 / AIN4 P6.3 / AIN3 P6.2 / AIN2 P6.1 / AIN1 P6.0 / AIN0 N.C. N.C. P3.0 / RxD P3.1 / TxD P3.2 / INT0 P3.3 / INT1 P3.4 / T0 P3.5 / T1 MCP03241 Figure 3 Pin Configuration P-MQFP-80 Package (top view) Semiconductor Group 6 1997-10-01 C515A Table 1 Pin Definitions and Functions Symbol P4.0-P4.7 Pin Number (P-MQFP-80) 72-74, 76-80 I/O*) Function I/O Port 4 is an 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port 4 pins that have 1's written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, port 4 pins being externally pulled low will source current (I IL, in the DC characteristics) because of the internal pull-up resistors. P4 also contains the external A/D converter control pin. The output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate. The secondary function is assigned to port 6 as follows: P4.0 / ADST external A/D converter start pin Power Saving Mode Enable / Start Watchdog Timer A low level on this pin allows the software to enter the power down, idle, and slow down mode. In case the low level is also seen during reset, the watchdog timer function is off on default. Use of the software controlled power saving modes is blocked when this pin is held on high level. A high level during reset performs an automatic start of the watchdog timer immediately after reset. When left unconnected this pin is pulled high by a weak internal pull-up resistor. Note: If PE/SWD is low and VAREF is low the oscillator watchdog is disabled (testmode)! RESET A low level on this pin for the duration of two machine cycles while the oscillator is running resets the C515A. A small internal pullup resistor permits power-on reset using only a capacitor connected to VSS . Reference Voltage for the A/D converter Reference Ground for the A/D converter Port 6 is an 8-bit unidirectional input port to the A/D converter. Port pins can be used for digital input, if voltage levels simultaneously meet the specifications for high/low input voltages and for the eight multiplexed analog inputs. 72 PE/SWD 75 I RESET 1 I VAREF VAGND P6.0-P6.7 3 4 12-5 - - I *) I = Input O = Output Semiconductor Group 7 1997-10-01 C515A Table 1 Pin Definitions and Functions (cont'd) Symbol P3.0-P3.7 Pin Number (P-MQFP-80) 15-22 I/O*) Function I/O Port 3 is an 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port 3 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 3 pins being externally pulled low will source current (I IL, in the DC characteristics) because of the internal pullup resistors. Port 3 also contains the interrupt, timer, serial port and external memory strobe pins that are used by various options. The output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate. The secondary functions are assigned to the pins of port 3, as follows: P3.0 / RxD Receiver data input (asynch.) or data input/output (synch.) of serial interface P3.1 / TxD Transmitter data output (asynch.) or clock output (synch.) of serial interface P3.2 / INT0 External interrupt 0 input / timer 0 gate control input P3.3 / INT1 External interrupt 1 input / timer 1 gate control input P3.4 / T0 Timer 0 counter input P3.5 / T1 Timer 1 counter input WR control output; latches P3.6 / WR the data byte from port 0 into the external data memory P3.7 / RD RD control output; enables the external data memory 15 16 17 18 19 20 21 22 *) I = Input O = Output Semiconductor Group 8 1997-10-01 C515A Table 1 Pin Definitions and Functions (cont'd) Symbol P1.0 - P1.7 Pin Number (P-MQFP-80) 31-24 I/O*) Function I/O Port 1 is an 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port 1 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 1 pins being externally pulled low will source current (I IL, in the DC characteristics) because of the internal pullup resistors. The port is used for the low-order address byte during program verification. Port 1 also contains the interrupt, timer, clock, capture and compare pins that are used by various options. The output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate (except when used for the compare functions). The secondary functions are assigned to the port 1 pins as follows: P1.0 / INT3 / CC0 Interrupt 3 input / compare 0 output / capture 0 input P1.1 / INT4 / CC1 Interrupt 4 input / compare 1 output / capture 1 input P1.2 / INT5 / CC2 Interrupt 5 input / compare 2 output / capture 2 input P1.3 / INT6 / CC3 Interrupt 6 input / compare 3 output / capture 3 input Interrupt 2 input P1.4 / INT2 P1.5 / T2EX Timer 2 external reload / trigger input P1.6 / CLKOUT System clock output P1.7 / T2 Counter 2 input Supply Voltage during normal, idle, and power down mode. Ground (0V) during normal, idle, and power down operation. 31 30 29 28 27 26 25 24 VCC VSS *) I = Input O = Output 32, 33 34, 35 - - Semiconductor Group 9 1997-10-01 C515A Table 1 Pin Definitions and Functions (cont'd) Symbol XTAL2 Pin Number (P-MQFP-80) 36 I/O*) Function - XTAL2 Input to the inverting oscillator amplifier and input to the internal clock generator circuits. To drive the device from an external clock source, XTAL2 should be driven, while XTAL1 is left unconnected. Minimum and maximum high and low times as well as rise/fall times specified in the AC characteristics must be observed. XTAL1 Output of the inverting oscillator amplifier. Port 2 is an 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port 2 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 2 pins being externally pulled low will source current (I IL, in the DC characteristics) because of the internal pullup resistors. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application it uses strong internal pullup resistors when issuing 1's. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), port 2 issues the contents of the P2 special function register. The Program Store Enable output is a control signal that enables the external program memory to the bus during external fetch operations. It is activated every six oscillator periods, except during external data memory accesses. The signal remains high during internal program execution. The Address Latch Enable output is used for latching the address into external memory during normal operation. It is activated every six oscillator periods, except during an external data memory access. ALE can be switched off when the program is executed internally. XTAL1 P2.0-P2.7 37 38-45 - I/O PSEN 47 O ALE 48 O *) I = Input O = Output Semiconductor Group 10 1997-10-01 C515A Table 1 Pin Definitions and Functions (cont'd) Symbol EA Pin Number (P-MQFP-80) 49 I/O*) Function I External Access Enable When held high, the C515A executes instructions from the internal ROM (C515A-4R) as long as the PC is less than 8000H. When held low, the C515A fetches all instructions from external program memory. For the C515A-L this pin must be tied low. Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1's written to them float, and in that state can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application it uses strong internal pullup resistors when issuing 1's. Port 0 also outputs the code bytes during program verification in the C515A-4R. External pullup resistors are required during program verification. Port 5 is an 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port 5 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 5 pins being externally pulled low will source current (I IL, in the DC characteristics) because of the internal pullup resistors. Hardware Power Down A low level on this pin for the duration of one machine cycle while the oscillator is running resets the C515A. A low level for a longer period will force the C515A into Hardware Power Down Mode with the pins floating. Not connected These pins of the P-MQFP-80 package need not be connected. P0.0-P0.7 52-59 I/O P5.0-P5.7 67-60 I/O HWPD 69 I N.C. 2, 13, 14, 23, 46, 50, 51, 68, 70, 71 - *) I = Input O = Output Semiconductor Group 11 1997-10-01 C515A Oscillator Watchdog XTAl1 OSC & Timing XTAL2 ALE PSEN EA PE / SWD RESET Timer 0 HWPD Timer 1 Programmable Watchdog Timer CPU RAM 256 x 8 XRAM 1Kx8 ROM 32 K x 8 Emulation Support Logic Port 0 8-Bit Digit. I / O Port 1 8-Bit Digit. I / O Port 2 8-Bit Digit. I / O Port 3 8-Bit Digit. I / O Port 4 8-Bit Digit. I / O Port 5 8-Bit Digit. I / O Port 6 8-Bit Analog / Digital Input Port 0 Port 1 Port 2 Timer 2 USART Baud Rate Generator Port 3 Port 4 Interrupt Unit Port 5 V AREF V AGND A/D Converter 10-Bit Analog MUX Port 6 S&H C515A MCB03242 Figure 4 Block Diagram of the C515A Semiconductor Group 12 1997-10-01 C515A CPU The C515A is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting of 44 % one-byte, 41 % two-byte, and 15% three-byte instructions. With a 18 MHz crystal, 58% of the instructions are executed in 666 ns (24 MHz : 500 ns). Special Function Register PSW (Address D0H) Bit No. MSB D7H D0H CY D6H AC D5H F0 D4H RS1 D3H RS0 D2H OV D1H F1 Reset Value : 00H LSB D0H P PSW Bit CY AC F0 RS1 RS0 Function Carry Flag Used by arithmetic instruction. Auxiliary Carry Flag Used by instructions which execute BCD operations. General Purpose Flag Register Bank select control bits These bits are used to select one of the four register banks. RS1 0 0 1 1 RS0 0 1 0 1 Function Bank 0 selected, data address 00H-07H Bank 1 selected, data address 08H-0FH Bank 2 selected, data address 10H-17H Bank 3 selected, data address 18H-1FH OV F1 P Overflow Flag Used by arithmetic instruction. General Purpose Flag Parity Flag Set/cleared by hardware after each instruction to indicate an odd/even number of "one" bits in the accumulator, i.e. even parity. Semiconductor Group 13 1997-10-01 C515A Memory Organization The C515A CPU manipulates operands in the following five address spaces: - - - - - up to 64 Kbyte of program memory (32K on-chip program memory for C515A-4R) up to 64 Kbyte of external data memory 256 bytes of internal data memory 1K bytes of internal XRAM data memory a 128 byte special function register area Figure 5 illustrates the memory address spaces of the C515A. Alternatively FFFF H Ext. Data Memory Ext. FBFF H 8000 H 7FFF H Ext. Data Memory Indirect Addr. Internal RAM Direct Addr. Special Function Regs. 80 H 7F H Internal RAM 0000 H "Code Space" "Data Space" 0000 H 00 H "Internal Data Space" MCB03243 FFFF H Internal XRAM (1 KByte) FC00 H FF H Int. EA = 1) Ext. EA = 1) Figure 5 C515A Memory Map Semiconductor Group 14 1997-10-01 C515A Reset and System Clock The reset input is an active low input at pin RESET. Since the reset is synchronized internally, the RESET pin must be held low for at least two machine cycles (24 oscillator periods) while the oscillator is running. A pullup resistor is internally connected to VCC to allow a power-up reset with an external capacitor only. An automatic reset can be obtained when VCC is applied by connecting the RESET pin to VSS via a capacitor. Figure 6 shows the possible reset circuitries. Figure 6 Reset Circuitries Semiconductor Group 15 1997-10-01 C515A Figure 7 shows the recommended oscillator circuitries for crystal and external clock operation. Crystal Oscillator Mode C XTAL1 3.5 - 24 MHz XTAL2 C Crystal Mode: C = 20 pF 10 pF (Incl. Stray Capacitance) Driving from External Source N.C. XTAL1 External Oscillator Signal XTAL2 MCS03245 Figure 7 Recommended Oscillator Circuitries Semiconductor Group 16 1997-10-01 C515A Enhanced Hooks Emulation Concept The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovative way to control the execution of C500 MCUs and to gain extensive information on the internal operation of the controllers. Emulation of on-chip ROM based programs is possible, too. Each production chip has built-in logic for the support of the Enhanced Hooks Emulation Concept. Therefore, no costly bond-out chips are necessary for emulation. This also ensure that emulation and production chips are identical. The Enhanced Hooks TechnologyTM 1), which requires embedded logic in the C500 allows the C500 together with an EH-IC to function similar to a bond-out chip. This simplifies the design and reduces costs of an ICE-system. ICE-systems using an EH-IC and a compatible C500 are able to emulate all operating modes of the different versions of the C500 microcontrollers. This includes emulation of ROM, ROM with code rollover and ROMless modes of operation. It is also able to operate in single step mode and to read the SFRs after a break. ICE-System interface to emulation hardware SYSCON PCON TCON C500 MCU opt. I/O Ports RESET EA ALE PSEN Port 0 Port 2 Port 3 Port 1 RSYSCON RPCON RTCON Enhanced Hooks Interface Circuit RPORT RPORT 2 0 TEA TALE TPSEN EH-IC Target System Interface MCS03254 Figure 8 Basic C500 MCU Enhanced Hooks Concept Configuration Port 0, port 2 and some of the control lines of the C500 based MCU are used by Enhanced Hooks Emulation Concept to control the operation of the device during emulation and to transfer informations about the program execution and data transfer between the external emulation hardware (ICE-system) and the C500 MCU. 1 "Enhanced Hooks Technology" is a trademark and patent of Metalink Corporation licensed to Siemens. Semiconductor Group 17 1997-10-01 C515A Special Function Registers The registers, except the program counter and the four general purpose register banks, reside in the special function register area. The special function register area consists of two portions: the standard special function register area and the mapped special function register area. One special function register of the C515A (PCON1) is located in the mapped special function register area. For accessing this mapped special function register, bit RMAP in special function register SYSCON must be set. All other special function registers are located in the standard special function register area which is accessed when RMAP is cleared ("0"). Special Function Register SYSCON (Address B1H) Bit No. MSB 7 B1H - Reset Value : XX10XX01B LSB 0 SYSCON 6 - 5 EALE 4 RMAP 3 - 2 - 1 XMAP1 XMAP0 The functions of the shaded bits are not described in this section. Bit RMAP Function Special function register map bit RMAP = 0: The access to the non-mapped (standard) special function register area is enabled. RMAP = 1: The access to the mapped special function register area (SFR PCON1) is enabled. Reserved bits for future use. Read by CPU returns undefined values. - As long as bit RMAP is set, the mapped special function register area (SFR PCON1) can be accessed. This bit is not cleared by hardware automatically. Thus, when non-mapped/mapped registers are to be accessed, the bit RMAP must be cleared/set respectively by software. The 49 special function registers (SFRs) in the standard and mapped SFR area include pointers and registers that provide an interface between the CPU and the other on-chip peripherals. All SFRs with addresses where address bits 0-2 are 0 (e.g. 80H, 88H, 90H, 98H, ..., F8H, FFH) are bitaddressable. The SFRs of the C515A are listed in table 2 and table 3. In table 2 they are organized in groups which refer to the functional blocks of the C515A. Table 3 illustrates the contents of the SFRs in numeric order of their addresses. Semiconductor Group 18 1997-10-01 C515A Table 2 Special Function Registers - Functional Blocks Block CPU Symbol ACC B DPH DPL PSW SP SYSCON 2) Name Accumulator B-Register Data Pointer, High Byte Data Pointer, Low Byte Program Status Word Register Stack Pointer System/XRAM Control Register A/D Converter Control Register 0 A/D Converter Control Register 1 A/D Converter Data Register, High Byte A/D Converter Data Register, low Byte Interrupt Enable Register 0 Interrupt Enable Register 1 Interrupt Priority Register 0 Interrupt Priority Register 1 Interrupt Request Control Register Timer Control Register Timer 2 Control Register Serial Channel Control Register Timer 0/1 Control Register Timer 0, High Byte Timer 1, High Byte Timer 0, Low Byte Timer 1, Low Byte Timer Mode Register Comp./Capture Enable Reg. Comp./Capture Reg. 1, High Byte Comp./Capture Reg. 2, High Byte Comp./Capture Reg. 3, High Byte Comp./Capture Reg. 1, Low Byte Comp./Capture Reg. 2, Low Byte Comp./Capture Reg. 3, Low Byte Com./Rel./Capt. Reg. High Byte Com./Rel./Capt. Reg. Low Byte Timer 2, High Byte Timer 2, Low Byte Timer 2 Control Register Address Contents after Reset E0H 1) F0H 1) 83H 82H D0H 1) 81H B1H D8H 1) DCH D9H DAH 4) A8H1) B8H 1) A9H B9H C0H 1) 88H 1) C8H 1) 98H 1) 88H 1) 8CH 8DH 8AH 8BH 89H C1H C3H C5H C7H C2H C4H C6H CBH CAH CDH CCH C8H 1) 00H 00H 00H 00H 00H 07H XX10 XX01B 3) 00H 0XXX X000B 3) 00H 00XX XXXXB 3) 00H 00H 00H XX00 0000B 3) 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H A/DADCON0 2) Converter ADCON1 ADDATH ADDATL Interrupt System IEN0 2) IEN1 2) IP0 2) IP1 2) IRCON TCON 2) T2CON 2) SCON 2) TCON 2) TH0 TH1 TL0 TL1 TMOD CCEN CCH1 CCH2 CCH3 CCL1 CCL2 CCL3 CRCH CRCL TH2 TL2 T2CON 2) Timer 0/ Timer 1 Compare/ Capture Unit / Timer 2 1) Bit-addressable special function registers 2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) "X" means that the value is undefined and the location is reserved Semiconductor Group 19 1997-10-01 C515A Table 2 Special Function Registers - Functional Blocks (cont'd) Block Ports Symbol P0 P1 P2 P3 P4 P5 P6 XPAGE SYSCON 2) Name Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6, Analog/Digital Input Page Address Register for Extended On-Chip RAM System/XRAM Control Register A/D Converter Control Register Power Control Register Serial Channel Buffer Register Serial Channel Control Register Serial Channel Reload Register, Low Byte Serial Channel Reload Register, High Byte Interrupt Enable Register 0 Interrupt Enable Register 1 Interrupt Priority Register 0 Interrupt Priority Register 1 Watchdog Timer Reload Register Power Control Register Power Control Register 1 Address Contents after Reset 80H 1) 90H 1) A0H 1) B0H 1 E8H 1) F8H 1) DBH 91H B1H D8H 1 87H 99H 98H 1) AAH BAH A8H1) B8H 1) A9H B9H 86H 87H 88H FFH FFH FFH FFH FFH FFH - 00H XX10 XX01B 3) 00H 00H XXH 3) 00H D9H XXXX XX11B 3) 00H 00H 00H XX00 0000B 3) 00H 00H 0XXX XXXXB 3) XRAM Serial Channel ADCON0 2) PCON 2) SBUF SCON 2) SRELL SRELH Watchdog IEN0 2) IEN1 2) IP0 2)) IP1 2) WDTREL Power Saving Modes PCON 2) PCON1 4) 1) Bit-addressable special function registers 2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) "X" means that the value is undefined and the location is reserved. 4) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. Semiconductor Group 20 1997-10-01 C515A Table 3 Contents of the SFRs, SFRs in numeric order of their addresses Addr Register Content Bit 7 after Reset1) 80H 2) P0 81H 82H 83H 86H 87H 88H 89H 8AH 8BH 8CH 8DH 3) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FFH 07H 00H 00H .7 .7 .7 .7 WDT PSEL TF1 .6 .6 .6 .6 .6 .5 .5 .5 .5 .5 IDLS TF0 - M1 .5 .5 .5 .5 T2EX .5 SM2 .5 .5 ET2 .5 T1 EALE .4 .4 .4 .4 .4 SD TR0 - M0 .4 .4 .4 .4 INT2 .4 REN .4 .4 ES .4 .4 T0 RMAP EX5 .4 .3 .3 .3 .3 .3 GF1 IE1 - GATE .3 .3 .3 .3 INT6 .3 TB8 .3 .3 ET1 .3 .3 INT1 - EX4 .3 .2 .2 .2 .2 .2 GF0 IT1 - C/T .2 .2 .2 .2 INT5 .2 RB8 .2 .2 EX1 .2 .2 INT0 - EX3 .2 .1 .1 .1 .1 .1 PDE IE0 - M1 .1 .1 .1 .1 INT4 .1 TI .1 .1 ET0 .1 .1 TxD .0 .0 .0 .0 .0 IDLE IT0 - M0 .0 .0 .0 .0 INT3 .0 RI .0 .0 EX0 .0 .0 RxD SP DPL DPH WDTREL 00H PCON PCON1 TMOD TL0 TL1 TH0 TH1 00H 00H 0XXXXXXXB 00H 00H 00H 00H 00H FFH 00H 00H XXH FFH 00H 00H D9H FFH SMOD PDS TR1 EWPD - GATE .7 .7 .7 .7 T2 .7 SM0 T2 .7 EAL .7 RD - C/T .6 .6 .6 .6 CLKOUT .6 SM1 .6 .6 WDT .6 WR - 88H 2) TCON 90H 2) P1 91H 99H A8H 2) XPAGE SBUF IEN0 IP0 98H 2) SCON A0H2) P2 A9H OWDS WDTS .5 AAH SRELL B0H2) P3 B1H SYSCON XX10XX01B IP1 00H XX000000B XMAP1 XMAP0 EX2 .1 EADC .0 B8H2) IEN1 B9H EXEN2 SWDT EX6 - - .5 1) X means that the value is undefined and the location is reserved 2) Bit-addressable special function registers 3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. Semiconductor Group 21 1997-10-01 C515A Table 3 Contents of the SFRs, SFRs in numeric order of their addresses (cont'd) Addr Register Content Bit 7 after Reset1) BAH SRELH C0H2) IRCON C1H C2H C3H C4H C5H C6H CCEN CCL1 CCH1 CCL2 CCH2 CCL3 XXXXXX11B 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H - EXF2 COCA H3 .7 .7 .7 .7 .7 .7 T2PS .7 .7 .7 .7 CY BD .9 .1 .7 ADCL .7 .7 .7 .7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - TF2 - IEX6 - IEX5 - IEX4 - IEX3 .1 IEX2 .0 IADC COCAL 0 .0 .0 .0 .0 .0 .0 T2I0 .0 .0 .0 .0 P MX0 .2 - .0 MX0 .0 .0 .0 .0 COCAL COCA 3 H2 .6 .6 .6 .6 .6 .6 I3FR .6 .6 .6 .6 AC CLK .8 .0 .6 - .6 .6 .6 .6 .5 .5 .5 .5 .5 .5 I2FR .5 .5 .5 .5 F0 ADEX .7 - .5 - .5 .5 .5 .5 COCAL COCA 2 H1 .4 .4 .4 .4 .4 .4 T2R1 .4 .4 .4 .4 RS1 BSY .6 - .4 - .4 .4 .4 .4 .3 .3 .3 .3 .3 .3 T2R0 .3 .3 .3 .3 RS0 ADM .5 - .3 - .3 .3 .3 .3 COCAL COCA 1 H0 .2 .2 .2 .2 .2 .2 T2CM .2 .2 .2 .2 OV MX2 .4 - .2 MX2 .2 .2 .2 .2 .1 .1 .1 .1 .1 .1 T2I1 .1 .1 .1 .1 F1 MX1 .3 - .1 MX1 .1 .1 .1 .1 C7H CCH3 C8H2) T2CON CAH CRCL CBH CRCH CCH TL2 CDH TH2 D0H2) PSW D8H2) D9H 00H ADCON0 00H ADDATH 00H DAH ADDATL 00XXXXXXB DBH P6 - DCH ADCON1 0XXXX000B E0H2) ACC E8H2) P4 F0H2) B F8H2) P5 00H 00H 00H FFH 1) X means that the value is undefined and the location is reserved 2) Bit-addressable special function registers Semiconductor Group 22 1997-10-01 C515A Digital I/O Ports The C515A allows for digital I/O on 48 lines grouped into 6 bidirectional 8-bit ports. Each port bit consists of a latch, an output driver and an input buffer. Read and write accesses to the I/O ports P0 through P5 are performed via their corresponding special function registers P0 to P5. The output drivers of port 0 and 2 and the input buffers of port 0 are also used for accessing external memory. In this application, port 0 outputs the low byte of the external memory address, timemultiplexed with the byte being written or read. Port 2 outputs the high byte of the external memory address when the address is 16 bits wide. Otherwise, the port 2 pins continue emitting the P2 SFR contents. Analog Input Ports Ports 6 is available as input port only and provides two functions. When used as digital inputs, the corresponding SFR P6 contains the digital value applied to the port 6 lines. When used for analog inputs the desired analog channel is selected by a three-bit field in SFR ADCON0. Of course, it makes no sense to output a value to these input-only ports by writing to the SFR P6. This will have no effect. If a digital value is to be read, the voltage levels are to be held within the input voltage specifications (VIL/VIH). Since P6 is not bit-addressable, all input lines of P6 are read at the same time by byte instructions. Nevertheless, it is possible to use port 6 simultaneously for analog and digital input. However, care must be taken that all bits of P6 that have an undetermined value caused by their analog function are masked. Semiconductor Group 23 1997-10-01 C515A Timer / Counter 0 and 1 Timer/Counter 0 and 1 can be used in four operating modes as listed in table 4: Table 4 Timer/Counter 0 and 1 Operating Modes Mode 0 1 2 3 Description 8-bit timer/counter with a divide-by-32 prescaler 16-bit timer/counter 8-bit timer/counter with 8-bit autoreload Timer/counter 0 used as one 8-bit timer/counter and one 8-bit timer Timer 1 stops TMOD M1 0 1 1 1 M0 0 1 0 internal Input Clock external (max) fOSC/12x32 fOSC/24x32 fOSC/12 1 fOSC/24 In the "timer" function (C/T = `0') the register is incremented every machine cycle. Therefore the count rate is fOSC/12. In the "counter" function the register is incremented in response to a 1-to-0 transition at its corresponding external input pin (P3.4/T0, P3.5/T1). Since it takes two machine cycles to detect a falling edge the max. count rate is fOSC/24. External inputs INT0 and INT1 (P3.2, P3.3) can be programmed to function as a gate to facilitate pulse width measurements. Figure 9 illustrates the input clock logic. f OSC / 12 C/T TMOD 0 f OSC/12 P3.4/T0 P3.5/T1 max f OSC/24 TR 0/1 TCON Gate TMOD P3.2/INT0 P3.3/INT1 =1 _ <1 Timer 0/1 Input Clock 1 Control & MCS01768 Figure 9 Timer/Counter 0 and 1 Input Clock Logic Semiconductor Group 24 1997-10-01 C515A Timer/Counter 2 with Compare/Capture/Reload The timer 2 of the C515A provides additional compare/capture/reload features. which allow the selection of the following operating modes: - Compare - Capture - Reload : up to 4 PWM signals with 16-bit/500 ns resolution : up to 4 high speed capture inputs with 500 ns resolution : modulation of timer 2 cycle time The block diagram in figure 10 shows the general configuration of timer 2 with the additional compare/capture/reload registers. The I/O pins which can used for timer 2 control are located as multifunctional port functions at port 1. P1.5/ T2EX P1.7/ T2 Sync. T2I0 T2I1 Sync. & / 12 Reload EXEN2 EXF2 _ <1 Interrupt Request Reload OSC f OSC / 24 T2PS Timer 2 TL2 TH2 TF2 Compare P1.0/ INT3/ CC0 P1.1/ INT4/ CC1 P1.2/ INT5/ CC2 P1.2/ INT6/ CC3 MCB03205 16 Bit Comparator 16 Bit Comparator 16 Bit Comparator 16 Bit Comparator Input/ Output Control Capture CCL3/CCH3 CCL2/CCH2 CCL1/CCH1 CRCL/CRCH Figure 10 Timer 2 Block Diagram Semiconductor Group 25 1997-10-01 C515A Timer 2 Operating Modes The timer 2, which is a 16-bit-wide register, can operate as timer, event counter, or gated timer. A roll-over of the count value in TL2/TH2 from all 1's to all 0's sets the timer overflow flag TF2 in SFR IRCON, which can generate an interrupt. The bits in register T2CON are used to control the timer 2 operation. Timer Mode: In timer function, the count rate is derived from the oscillator frequency. A prescaler offers the possibility of selecting a count rate of 1/12 or 1/24 of the oscillator frequency. Gated Timer Mode: In gated timer function, the external input pin T2 (P1.7) functions as a gate to the input of timer 2. If T2 is high, the internal clock input is gated to the timer. T2 = 0 stops the counting procedure. This facilitates pulse width measurements. The external gate signal is sampled once every machine cycle. Event Counter Mode: In the event counter function. the timer 2 is incremented in response to a 1-to-0 transition at its corresponding external input pin T2 (P1.7). In this function, the external input is sampled every machine cycle. Since it takes two machine cycles (24 oscillator periods) to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. There are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it must be held for at least one full machine cycle. Reload of Timer 2: Two reload modes are selectable: In mode 0, when timer 2 rolls over from all 1's to all 0's, it not only sets TF2 but also causes the timer 2 registers to be loaded with the 16-bit value in the CRC register, which is preset by software. In mode 1, a 16-bit reload from the CRC register is caused by a negative transition at the corresponding input pin P1.5/T2EX. This transition will also set flag EXF2 if bit EXEN2 in SFR IEN1 has been set. Semiconductor Group 26 1997-10-01 C515A Timer 2 Compare Modes The compare function of a timer/register combination operates as follows: the 16-bit value stored in a compare or compare/capture register is compared with the contents of the timer register; if the count value in the timer register matches the stored value, an appropriate output signal is generated at a corresponding port pin and an interrupt can be generated. Compare Mode 0 In compare mode 0, upon matching the timer and compare register contents, the output signal changes from low to high. It goes back to a low level on timer overflow. As long as compare mode 0 is enabled, the appropriate output pin is controlled by the timer circuit only and writing to the port will have no effect. Figure 11 shows a functional diagram of a port circuit when used in compare mode 0. The port latch is directly controlled by the timer overflow and compare match signals. The input line from the internal bus and the write-to-latch line of the port latch are disconnected when compare mode 0 is enabled. Port Circuit Read Latch Compare Register Circuit Compare Reg. 16 Bit Comparator 16 Bit Timer Register Timer Circuit Timer Overflow Read Pin MCS02661 VCC Compare Match Internal Bus Write to Latch S D Q Port Latch CLK Q R Port Pin Figure 11 Port Latch in Compare Mode 0 Semiconductor Group 27 1997-10-01 C515A Compare Mode 1 If compare mode 1 is enabled and the software writes to the appropriate output latch at the port, the new value will not appear at the output pin until the next compare match occurs. Thus, it can be choosen whether the output signal has to make a new transition (1-to-0 or 0-to-1, depending on the actual pin-level) or should keep its old value at the time when the timer value matches the stored compare value. In compare mode 1 (see figure 12) the port circuit consists of two separate latches. One latch (which acts as a "shadow latch") can be written under software control, but its value will only be transferred to the port latch (and thus to the port pin) when a compare match occurs. Port Circuit Read Latch Compare Register Circuit Compare Reg. 16 Bit Comparator 16 Bit Timer Register Timer Circuit Read Pin MCS02662 VCC Internal Bus Compare Match Write to Latch D Shadow Latch CLK Q D Q Port Latch CLK Q Port Pin Figure 12 Compare Function in Compare Mode 1 Semiconductor Group 28 1997-10-01 C515A Serial Interface (USART) The serial port is full duplex and can operate in four modes (one synchronous mode, three asynchronous modes) as illustrated in table 5. The possible baudrates can be calculated using the formulas given in table 5. Table 5 USART Operating Modes Mode 0 SCON SM0 0 SM1 0 Shift register mode Serial data enters and exits through RxD/ TxD outputs the shift clock; 8-bit are transmitted/received (LSB first); fixed baud rate 8-bit UART, variable baud rate 10 bits are transmitted (through TxD) or received (at RxD) 9-bit UART, fixed baud rate 11 bits are transmitted (through TxD) or received (at RxD) 9-bit UART, variable baud rate Like mode 2 Description 1 2 3 0 1 1 1 0 1 For clarification some terms regarding the difference between "baud rate clock" and "baud rate" should be mentioned. In the asynchronous modes the serial interfaces require a clock rate which is 16 times the baud rate for internal synchronization. Therefore, the baud rate generators/timers have to provide a "baud rate clock" (output signal in figure 13 to the serial interface which - there divided by 16 - results in the actual "baud rate". Further, the abbreviation fOSC refers to the oscillator frequency (crystal or external clock operation). The variable baud rates for modes 1 and 3 of the serial interface can be derived from either timer 1 or a dedicated baud rate generator (see figure 13). Semiconductor Group 29 1997-10-01 C515A Figure 13 Block Diagram of Baud Rate Generation for the Serial Interface Table 6 below lists the values/formulas for the baud rate calculation of the serial interface with its dependencies of the control bits BD and SMOD. Table 6 Serial Interface - Baud Rate Dependencies Serial Interface 0 Operating Modes Mode 0 (Shift Register) Mode 1 (8-bit UART) Mode 3 (9-bit UART) Active Control Bits Baud Rate Calculation BD - 0 1 SMOD - X X fOSC / 12 Controlled by timer 1 overflow: (2SMOD x timer 1 overflow rate) / 32 Controlled by baud rate generator (2SMOD x fOSC) / (64 x baud rate generator overflow rate) Mode 2 (9-bit UART) - 0 1 fOSC / 64 fOSC / 32 Semiconductor Group 30 1997-10-01 C515A 10-Bit A/D Converter The C515A provides an A/D converter with the following features: - - - - - - - 8 multiplexed input channels (port 6), which can also be used as digital inputs 10-bit resolution Single or continuous conversion mode Internal or external start-of-conversion trigger capability Interrupt request generation after each conversion Using successive approximation conversion technique via a capacitor array Built-in hidden calibration of offset and linearity errors The A/D converter operates with a successive approximation technique and uses self calibration mechanisms for reduction and compensation of offset and linearity errors. The externally applied reference voltage range has to be held on a fixed value within the specifications. The main functional blocks of the A/D converter are shown in figure 14. Semiconductor Group 31 1997-10-01 C515A IEN1 (B8 H ) EXEN2 SWDT EX6 EX5 EX4 EX3 EX2 EADC Internal Bus IRCON (C0 H ) EXF2 TF2 IEX6 IEX5 IEX4 IEX3 IEX2 IADC ADCON1 (DC H ) ADCL ADCON0 (D8 H ) BD CLK ADEX BSY ADM MX2 MX1 MX0 MX2 MX1 MX0 ADDATH ADDATL (D9 H ) (DA H ) Port 6 MUX S&H Clock Prescaler 8, 4 Single/ Continuous Mode .2 .3 .4 .5 .6 .7 .8 MSB LSB .1 f OSC /2 Conversion Clock f ADC Input Clock f IN A/D Converter V AREF V AGND Start of conversion Internal Bus P4.0 / ADST Shaded Bit locations are not used in ADC-functions. Write to ADDATL MCB03247 Figure 14 A/D Converter Block Diagram Semiconductor Group 32 1997-10-01 C515A Interrupt System The C515A provides 12 interrupt sources with four priority levels. Five interrupts can be generated by the on-chip peripherals (timer 0, timer 1, timer 2, A/D converter, and serial interface) and seven interrupts may be triggered externally (P3.2/INT0, P3.3/INT1, P1.4/INT2, P1.0/INT3, P1.1/INT4, P1.2/INT5, P1.3/INT6). The wake-up from power-down mode interrupt has a special functionality which allows to exit from the software power-down mode by a short low pulse at pin P3.2/INT0. This chapter shows the interrupt structure, the interrupt vectors and the interrupt related special function registers. Figure 15 and 16 give a general overview of the interrupt sources and illustrate the request and the control flags which are described in the next sections. Semiconductor Group 33 1997-10-01 C515A Highest Priority Level P3.2 INT0 IT0 TCON.0 A / D Converter IADC IRCON.0 EADC IEN1.0 IE0 TCON.1 EX0 IEN0.0 0003 H Lowest Priority Level 0043 H IP1.0 IP0.0 P o l l i n g S e q u e n c e Timer 0 Overflow TF0 TCON.5 ET0 IEN0.1 000B H P1.4 / NT2 I2FR T2CON.5 P3.3 / INT1 IT1 TCON.2 P1.0 / INT3 CC0 I3FR T2CON.6 Bit addressable Request flag is cleared by hardware IEX3 IRCON.2 EX3 IEN1.2 0013 H EAL IEN0.7 IP1.2 IP0.2 IEX2 IRCON.1 EX2 IEN1.1 004B H IP1.1 IP0.1 IE1 TCON.3 EX1 IEN0.2 0013 H MCB03248 Figure 15 Interrupt Request Sources (Part 1) Semiconductor Group 34 1997-10-01 C515A Highest Priority Level Timer 1 Overflow TF1 TCON.7 ET1 IEN0.3 P1.1 / INT4 / CC1 IEX4 IRCON.3 EX4 IEN1.3 SCON.0 RI USART TI SCON.1 P1.2 / INT5 / CC2 IEX5 IRCON.4 EX5 IEN1.4 Timer 2 Overflow P1.5/ T2EX EXEN2 P1.3 / INT6 / CC3 IEN1.7 IEX6 IRCON.5 Bit addressable Request flag is cleared by hardware ET6 IEN1.5 006B H EAL IEN0.7 MCB03249 001B H Lowest Priority Level 005B H IP1.3 IP0.3 P o l l i n g S e q u e n c e <1 ES IEN0.4 0023 H 0063 H IP1.4 IP0.4 IRCON.6 TF2 EXF2 IRCON.7 <1 ET2 IEN0.5 002B H IP1.5 IP0.5 Figure 16 Interrupt Request Sources (Part 2) Semiconductor Group 35 1997-10-01 C515A Table 7 Interrupt Source and Vectors Interrupt Source External Interrupt 0 Timer 0 Overflow External Interrupt 1 Timer 1 Overflow Serial Channel Timer 2 Overflow / Ext. Reload A/D Converter External Interrupt 2 External Interrupt 3 External Interrupt 4 External Interrupt 5 External Interrupt 6 Wake-up from power-down mode Interrupt Vector Address 0003H 000BH 0013H 001BH 0023H 002BH 0043H 004BH 0053H 005BH 0063H 006BH 007BH Interrupt Request Flags IE0 TF0 IE1 TF1 RI / TI TF2 / EXF2 IADC IEX2 IEX3 IEX4 IEX5 IEX6 - Semiconductor Group 36 1997-10-01 C515A Fail Save Mechanisms The C515A offers enhanced fail safe mechanisms, which allow an automatic recovery from software upset or hardware failure: - a programmable watchdog timer (WDT), with variable time-out period from 512 s up to approx. 1.1 s at 12 MHz (256 s up to approx. 0.65 s at 24 MHz) - an oscillator watchdog (OWD) which monitors the on-chip oscillator and forces the microcontroller into reset state in case the on-chip oscillator fails; it also provides the clock for a fast internal reset after power-on. The watchdog timer in the C515A is a 15-bit timer, which is incremented by a count rate of fOSC/24 up to fOSC/384. The system clock of the C515A is divided by two prescalers, a divide-by-two and a divide-by-16 prescaler. For programming of the watchdog timer overflow rate, the upper 7 bit of the watchdog timer can be written. Figure 15 shows the block diagram of the watchdog timer unit. 0 7 WDTL 14 8 WDTH f OSC /12 2 16 WDT Reset-Request IP0 (A9 H ) WDTS - - - - - - WDTPSEL External HW Reset External HW Power-Down PE/SWD 76 WDTREL (86 H ) IEN0 (A8 )H IEN1 (B8 )H MCB03250 0 Control Logic WDT SWDT - - - Figure 17 Block Diagram of the Watchdog Timer The watchdog timer can be started by software (bit SWDT) or by hardware through pin PE/SWD, but it cannot be stopped during active mode of the C515A. If the software fails to refresh the running watchdog timer an internal reset will be initiated on watchdog timer overflow. For refreshing of the watchdog timer the content of the SFR WDTREL is transferred to the upper 7-bit of the watchdog timer. The refresh sequence consists of two consecutive instructions which set the bits WDT and SWDT each. The reset cause (external reset or reset caused by the watchdog) can be examined by software (flag WDTS). It must be noted, however, that the watchdog timer is halted during the idle mode and power down mode of the processor. Semiconductor Group 37 1997-10-01 C515A Oscillator Watchdog The oscillator watchdog unit serves for four functions: - Monitoring of the on-chip oscillator's function The watchdog supervises the on-chip oscillator's frequency; if it is lower than the frequency of the auxiliary RC oscillator in the watchdog unit, the internal clock is supplied by the RC oscillator and the device is brought into reset; if the failure condition disappears (i.e. the on-chip oscillator has a higher frequency than the RC oscillator), the part executes a final reset phase of typ. 1 ms in order to allow the oscillator to stabilize; then the oscillator watchdog reset is released and the part starts program execution again. - Fast internal reset after power-on The oscillator watchdog unit provides a clock supply for the reset before the on-chip oscillator has started. The oscillator watchdog unit also works identically to the monitoring function. - Restart from the hardware power down mode. If the hardware power down mode is terminated the oscillator watchdog has to control the correct start-up of the on-chip oscillator and to restart the program. The oscillator watchdog function is only part of the complete hardware power down sequence; however, the watchdog works identically to the monitoring function. - Control of external wake-up from software power-down mode When the software power-down mode is left by a low level at the P3.2/INT0 pin, the oscillator watchdog unit assures that the microcontroller resumes operation (execution of the power-down wake-up interrupt) with the nominal clock rate. In the power-down mode the RC oscillator and the on-chip oscillator are stopped. Both oscillators are started again when power-down mode is released. When the on-chip oscillator has a higher frequency than the RC oscillator, the microcontroller starts operation after a final delay of typ. 1 ms in order to allow the on-chip oscillator to stabilize. Semiconductor Group 38 1997-10-01 C515A EWPD (PCON1.0) Power-Down Mode Activated Power-Down Mode Wake-Up Interrupt P3.2 / INT0 Control Logic Start / Stop RC Oscillator Control Logic Internal Reset f RC 3 MHz Start / Stop 5 f1 Frequency Comparator f 2 >1 XTAL1 XTAL2 On-Chip Oscillator f2 IP0 (A9 H ) OWDS 2 Int. Clock MCB03251 Figure 18 Block Diagram of the Oscillator Watchdog Semiconductor Group 39 1997-10-01 C515A Power Saving Modes The C515A provides two basic power saving modes, the idle mode and the power down mode. Additionally, a slow down mode is available. This power saving mode reduces the internal clock rate in normal operating mode and it can be also used for further power reduction in idle mode. - Idle mode The CPU is gated off from the oscillator. All peripherals are still provided with the clock and are able to work. Idle mode is entered by software and can be left by an interrupt or reset. - Slow down mode The controller keeps up the full operating functionality, but its normal clock frequency is internally divided by 8. This slows down all parts of the controller, the CPU and all peripherals, to 1/8th of their normal operating frequency and also reduces power consumption. - Software power down mode The operation of the C515 is completely stopped and the oscillator is turned off. This mode is used to save the contents of the internal RAM with a very low standby current. This power down mode is entered by software and can be left by reset or by a short low pulse at pin P3.2/ INT0. - Hardware Power down mode If pin HWPD gets active (low level) the part enters the hardware power down mode and starts a complete internal reset sequence. Thereafter, both oscillators of the chip are stopped and the port pins and several control lines enter a floating state. In the power down mode of operation, VCC can be reduced to minimize power consumption. It must be ensured, however, that VCC is not reduced before the power down mode is invoked, and that VCC is restored to its normal operating level, before the power down mode is terminated. Table 8 gives a general overview of the entry and exit procedures of the power saving modes. Semiconductor Group 40 1997-10-01 C515A Table 8 Power Saving Modes Overview Mode Entering 2-Instruction Example ORL PCON, #01H ORL PCON, #20H Leaving by Remarks Idle mode Occurrence of an interrupt from a peripheral unit Hardware Reset CPU clock is stopped; CPU maintains their data; peripheral units are active (if enabled) and provided with clock Internal clock rate is reduced to 1/8 of its nominal frequency CPU clock is stopped; CPU maintains their data; peripheral units are active (if enabled) and provided with 1/8 of its nominal frequency Oscillator is stopped; contents of on-chip RAM and SFR's are maintained; Oscillator is stopped; internal reset is executed; Slow Down Mode In normal mode: ORL PCON,#10H With idle mode: ORL PCON,#01H ORL PCON, #30H ANL PCON,#0EFH or Hardware Reset Occurrence of an interrupt from a peripheral unit Hardware reset Software Power Down Mode Hardware Power Down Mode ORL PCON, #02H ORL PCON, #40H HWPD = 0 Hardware Reset Short low pulse at pin P3.2/INT0 HWPD = 1 Semiconductor Group 41 1997-10-01 C515A Absolute Maximum Ratings Ambient temperature under bias (TA) ......................................................... Storage temperature (Tstg) .......................................................................... Voltage on VCC pins with respect to ground (VSS) ....................................... Voltage on any pin with respect to ground (VSS) ......................................... Input current on any pin during overload condition..................................... Absolute sum of all input currents during overload condition ..................... Power dissipation of package ..................................................................... - 40 to + 125 C - 65 C to 150 C - 0.5 V to 6.5 V - 0.5 V to VCC +0.5 V - 10 mA to 10 mA I 100 mA I TBD Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for longer periods may affect device reliability. During overload conditions (VIN > VCC or VIN < VSS) the Voltage on VCC pins with respect to ground (VSS) must not exceed the values defined by the absolute maximum ratings. Semiconductor Group 42 1997-10-01 C515A DC Characteristics VCC = 5 V + 10%, - 15%; VSS = 0 V TA = 0 to 70 C TA = - 40 to 85 C TA = - 40 to 110 C TA = - 40 to 125 C Limit Values min. max. for the SAB-C515A for the SAF-C515A for the SAH-C515A for the SAK-C515A Unit Test Condition Parameter Input low voltage Pins except EA,RESET,HWPD EA pin HWPD and RESET pins Input high voltage pins except RESET, XTAL2 and HWPD XTAL2 pin RESET and HWPD pin Output low voltage Ports 1, 2, 3, 4, 5 Port 0, ALE, PSEN Output high voltage Ports 1, 2, 3, 4, 5 Port 0 in external bus mode, ALE, PSEN Logic 0 input current Ports 1, 2, 3, 4, 5 Logical 0-to-1 transition current, Ports 1, 2, 3, 4, 5 Input leakage current Port 0 and 6, EA, HWPD Input low current to RESET for reset XTAL2 PE/SWD Pin capacitance Overload current Notes see next page Symbol VIL VIL1 VIL2 - 0.5 - 0.5 - 0.5 0.2 VCC - 0.1 V 0.2 VCC - 0.3 V 0.2 VCC + 0.1 V - - - VIH VIH1 VIH2 VOL VOL1 VOH VOH1 0.2 VCC + 0.9 VCC + 0.5 0.7 VCC VCC + 0.5 0.6 VCC VCC + 0.5 - - 2.4 0.9 VCC 2.4 0.9 VCC - 10 - 65 - - 10 - - - - 0.45 0.45 - - - - - 70 - 650 V V V V V V V V V A A A A A A pF mA - - - I OL = 1.6 mA 1) I OL = 3.2 mA 1) I OH = - 80 A I OH = - 10 A I OH = - 800 A2) I OH = - 80 A 2) V I N = 0.45 V V IN = 2 V 0.45 < V I N < VCC VI N = 0.45 V V I N = 0.45 V V I N = 0.45 V f C = 1 MHz, T A = 25 C 8) 9) I LI I TL I LI I IL2 I IL3 I IL4 C IO IOV 1 - 100 - 15 - 20 10 5 Semiconductor Group 43 1997-10-01 C515A Power Supply Current Parameter Active mode Idle mode Active mode with slow-down enabled Active mode with slow-down enabled Power-down mode Notes: 1) Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOL of ALE and port 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operation. In the worst case (capacitive loading > 100 pF), the noise pulse on ALE line may exceed 0.8 V. In such cases it may be desirable to qualify ALE with a schmitt-trigger, or use an address latch with a schmitt-trigger strobe input. 2) Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9 VCC specification when the address lines are stabilizing. 3) IPD (software power-down mode) is measured under following conditions: EA = RESET = Port 0 = Port 6 = V CC ; XTAL1 = N.C.; XTAL2 = V SS ; PE/SWD = V SS ; HWPD = V CC ; VAGND = VSS ; VAREF = VCC ; all other pins are disconnected. IPD (hardware power-down mode): independent from any particular pin connection. 4) ICC (active mode) is measured with: XTAL2 driven with tCLCH , tCHCL = 5 ns , VIL = VSS + 0.5 V, VIH = VCC - 0.5 V; XTAL1 = N.C.; EA = PE/SWD = Port 0 = Port 6 = VCC ; HWPD = VCC ; RESET = VSS ; all other pins are disconnected. ICC would be slightly higher if a crystal oscillator is used (appr. 1 mA). 5) ICC (idle mode) is measured with all output pins disconnected and with all peripherals disabled; XTAL2 driven with tCLCH , tCHCL = 5 ns, VIL = VSS + 0.5 V, VIH = VCC - 0.5 V; XTAL1 = N.C.; RESET = VCC ; HWPD = Port 0 = Port 6 = VCC ; EA = PE/SWD = VSS ; all other pins are disconnected; 6) ICC (active mode with slow-down mode) is measured with all output pins disconnected and with all peripherals disabled; XTAL2 driven with tCLCH , tCHCL = 5 ns, VIL = VSS + 0.5 V, VIH = VCC - 0.5 V; XTAL1 = N.C.; RESET = V CC ; HWPD = Port 6 = V CC ; EA = PE/SWD = V SS ; all other pins are disconnected; the microcontroller is put into slow-down mode by software; 7) ICC (idle mode with slow-down mode) is measured with all output pins disconnected and with all peripherals disabled; XTAL2 driven with tCLCH , tCHCL = 5 ns, VIL = VSS + 0.5 V, VIH = VCC - 0.5 V; XTAL1 = N.C.; RESET = VCC ; HWPD = Port 6 = VCC ; EA = PE/SWD = VSS ; all other pins are disconnected; the microcontroller is put into idle mode with slow-down mode enabled by software; 8) Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin exceeds the specified range (i.e. VOV > VCC + 0.5 V or VOV < VSS - 0.5 V). The supply voltage VCC and VSS must remain within the specified limits. The absolute sum of input currents on all port pins may not exceed 50 mA. 9) Not 100% tested, guaranteed by design characterization 10)The typical ICC values are periodically measured at TA = +25 C and VCC = 5 V but not 100% tested. 11)The maximum ICC values are measured under worst case conditions (TA = 0 C or -40 C and VCC = 5.5 V) Symbol 18 MHz 24 MHz 18 MHz 24 MHz 18 MHz 24 MHz 18 MHz 24 MHz Limit Values typ. 10) max. 11) 23.1 29.4 12.1 15.0 8.0 9.6 4.1 4.7 50 16.9 21.7 8.5 11.0 5.6 6.6 3.0 3.3 10 Unit Test Condition mA mA mA mA mA mA mA mA A 4) ICC ICC ICC ICC ICC ICC ICC ICC IPD 5) 6) 7) VCC = 2...5.5 V 3) Semiconductor Group 44 1997-10-01 C515A 30 mA MCD03252 CC 25 20 15 10 CC max CC typ Active Mode Active Mode Idle Mode Idle Mode Active + Slow Down Mode 5 0 0 4 8 12 16 Idle + Slow Down Mode 20 MHz f OSC 24 Figure 19 ICC Diagram Table 9 Power Supply Current Calculation Formulas Parameter Active mode Idle mode Active mode with slow-down enabled Idle mode with slow-down enabled Symbol Formula 0.79 * fOSC + 2.7 1.04 * fOSC + 4.4 0.43 * fOSC + 0.7 0.48 * fOSC + 3.5 0.17 * fOSC + 2.5 0.28 * fOSC + 2.9 0.06 * fOSC + 1.9 0.09 * fOSC + 2.5 ICC typ ICC max ICC typ ICC max ICC typ ICC max ICC typ ICC max Note: fosc is the oscillator frequency in MHz. ICC values are given in mA. Semiconductor Group 45 1997-10-01 C515A A/D Converter Characteristics VCC = 5 V + 10%, - 15%; VSS = 0 V TA = 0 to 70 C TA = - 40 to 85 C TA = - 40 to 110 C TA = - 40 to 125 C for the SAB-C515A for the SAF-C515A for the SAH-C515A for the SAK-C515A 4 V VAREF VCC + 0.1 V; VSS - 0.1 V VAGND VSS + 0.2 V Parameter Analog input voltage Sample time Conversion cycle time Total unadjusted error Symbol Limit Values min. max. Unit V ns ns LSB Test Condition 1) VAIN tS tADCC TUE VAGND - - - - - - VAREF 16 x tIN 8 x tIN 96 x tIN 48 x tIN 2 -1 Prescaler / 8 Prescaler / 4 Prescaler / 8 Prescaler / 4 2) 3) Internal resistance of RAREF reference voltage source Internal resistance of analog source ADC input capacitance Notes see next page. tADC / 250 k tS / 500 - 0.8 50 k pF VSS + 0.5 V VIN VCC - 0.5 V 4) tADC in [ns] 5) 6) tS in [ns] 6) 2) 6) RASRC CAIN Clock calculation table: Clock Prescaler ADCL Ratio /8 /4 1 0 tADC 8 x tIN 4 x tIN tS 16 x tIN 8 x tIN tADCC 96 x tIN 48 x tIN Further timing conditions: tADC min = 500 ns tIN = 2 / fOSC = 2 tCLCL Semiconductor Group 46 1997-10-01 C515A Notes: 1) VAIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in these cases will be X000H or X3FFH, respectively. 2) During the sample time the input capacitance CAIN can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach their final voltage level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion result. 3) This parameter includes the sample time tS, the time for determining the digital result and the time for the calibration. Values for the conversion clock tADC depend on programming and can be taken from the table on the previous page. 4) TUE is tested at VAREF = 5.0 V, VAGND = 0 V, VCC = 4.9 V. It is guaranteed by design characterization for all other voltages within the defined voltage range. If an overload condition occurs on maximum 2 not selected analog input pins and the absolute sum of input overload currents on all analog input pins does not exceed 10 mA, an additional conversion error of 1/2 LSB is permissible. 5) During the conversion the ADC's capacitance must be repeatedly charged or discharged. The internal resistance of the reference source must allow the capacitance to reach their final voltage level within the indicated time. The maximum internal resistance results from the programmed conversion timing. 6) Not 100% tested, but guaranteed by design characterization. Semiconductor Group 47 1997-10-01 C515A AC Characteristics (18 MHz) VCC = 5 V + 10%, - 15%; VSS = 0 V TA = 0 to 70 C TA = - 40 to 85 C TA = - 40 to 110 C TA = - 40 to 125 C for the SAB-C515A for the SAF-C515A for the SAH-C515A for the SAK-C515A (CL for port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF) Program Memory Characteristics Parameter Symbol 18 MHz Clock min. ALE pulse width Address setup to ALE Address hold after ALE ALE low to valid instruction in ALE to PSEN PSEN pulse width PSEN to valid instruction in Input instruction hold after PSEN Input instruction float after PSEN Address valid after PSEN Address to valid instr in Address float to PSEN *) Limit Values Variable Clock 1/tCLCL = 3.5 MHz to 18 MHz min. 2 tCLCL - 40 max. - - - 4 tCLCL - 100 - - 3 tCLCL - 75 - Unit max. - - - 122 - - 92 - 46 - 180 - tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ*) tPXAV tAVIV tAZPL *) 71 26 26 - 31 132 - 0 - 48 - 0 ns ns ns ns ns ns ns ns ns ns ns ns tCLCL - 30 tCLCL - 30 - tCLCL - 25 3 tCLCL - 35 - 0 - tCLCL - 10 - 5 tCLCL - 98 - tCLCL - 8 - 0 Interfacing the C515A to devices with float times up to 48 ns is permissible. This limited bus contention will not cause any damage to port 0 drivers. Semiconductor Group 48 1997-10-01 C515A AC Characteristics (18 MHz, cont'd) External Data Memory Characteristics Parameter Symbol 18 MHz Clock min. RD pulse width WR pulse width Address hold after ALE RD to valid data in Data hold after RD Data float after RD ALE to valid data in Address to valid data in ALE to WR or RD Address valid to WR or RD WR or RD high to ALE high Data valid to WR transition Data setup before WR Data hold after WR Address float after RD max. - - - 128 - 51 294 335 217 - 96 - - - 0 Limit Values Variable Clock 1/tCLCL = 3.5 MHz to 18 MHz min. 6 tCLCL - 100 6 tCLCL - 100 2 tCLCL - 30 - 0 - - - 3 tCLCL - 50 4 tCLCL - 130 max. - - - 5 tCLCL - 150 - 2 tCLCL - 60 8 tCLCL - 150 9 tCLCL - 165 3 tCLCL + 50 - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit tRLRH tWLWH tLLAX2 tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tWHLH tQVWX tQVWH tWHQX tRLAZ 233 233 81 - 0 - - - 117 92 16 11 239 16 - tCLCL - 40 tCLCL - 45 7 tCLCL - 150 tCLCL + 40 - - - 0 tCLCL - 40 - External Clock Drive Characteristics Parameter Symbol Limit Values Variable Clock Freq. = 3.5 MHz to 18 MHz min. Oscillator period High time Low time Rise time Fall time max. 285.7 ns ns ns ns ns Unit tCLCL tCHCX tCLCX tCLCH tCHCL 55.6 15 15 - - tCLCL - tCLCX tCLCL - tCHCX 15 15 Semiconductor Group 49 1997-10-01 C515A AC Characteristics (24 MHz) VCC = 5 V + 10%, - 15%; VSS = 0 V TA = 0 to 70 C TA = - 40 to 85 C TA = - 40 to 110 C for the SAB-C515A for the SAF-C515A for the SAH-C515A (CL for port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF) Program Memory Characteristics Parameter Symbol 24 MHz Clock min. ALE pulse width Address setup to ALE Address hold after ALE ALE low to valid instruction in ALE to PSEN PSEN pulse width PSEN to valid instruction in Input instruction hold after PSEN Input instruction float after PSEN Address valid after PSEN Address to valid instr in Address float to PSEN *) Limit Values Variable Clock 1/tCLCL = 3.5 MHz to 24 MHz min. 2 tCLCL - 40 max. - - - 4 tCLCL - 87 - - 3 tCLCL - 65 - Unit max. - - - 80 - - 60 - 32 - 148 - tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ*) tPXAV*) tAVIV tAZPL 43 17 17 - 22 95 - 0 - 37 - 0 ns ns ns ns ns ns ns ns ns ns ns ns tCLCL - 25 tCLCL - 25 - tCLCL - 20 3tCLCL - 30 - 0 - tCLCL - 10 - 5 tCLCL - 60 - tCLCL - 5 - 0 Interfacing the C515A to devices with float times up to 37 ns is permissible. This limited bus contention will not cause any damage to port 0 drivers. Semiconductor Group 50 1997-10-01 C515A AC Characteristics (24 MHz, cont'd) External Data Memory Characteristics Parameter Symbol 24 MHz Clock min. RD pulse width WR pulse width Address hold after ALE RD to valid data in Data hold after RD Data float after RD ALE to valid data in Address to valid data in ALE to WR or RD Address valid to WR or RD WR or RD high to ALE high Data valid to WR transition Data setup before WR Data hold after WR Address float after RD max. - - - 118 - 63 200 220 175 - 67 - - - 0 Limit Values Variable Clock 1/tCLCL = 3.5 MHz to 24 MHz min. 6 tCLCL - 70 6 tCLCL - 70 max. - - - 5 tCLCL - 90 - 2 tCLCL - 20 8 tCLCL - 133 9 tCLCL - 155 3 tCLCL + 50 - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit tRLRH tWLWH tLLAX2 tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tWHLH tQVWX tQVWH tWHQX tRLAZ 180 180 56 - 0 - - - 75 67 17 5 170 15 - 2 tCLCL - 27 - 0 - - - 3 tCLCL - 50 4 tCLCL - 97 tCLCL - 25 tCLCL - 37 7 tCLCL - 122 tCLCL + 25 - - - 0 tCLCL - 27 - External Clock Drive Characteristics Parameter Symbol Limit Values Variable Clock Freq. = 3.5 MHz to 24 MHz min. Oscillator period High time Low time Rise time Fall time max. 285.7 ns ns ns ns ns Unit tCLCL tCHCX tCLCX tCLCH tCHCL 41.7 12 12 - - tCLCL - tCLCX tCLCL - tCHCX 12 12 Semiconductor Group 51 1997-10-01 C515A t LHLL ALE t AVLL t LLIV t PLPH t LLPL t PLIV PSEN t AZPL t LLAX t PXAV t PXIZ t PXIX Port 0 A0 - A7 Instr.IN A0 - A7 t AVIV Port 2 A8 - A15 A8 - A15 MCT00096 Figure 20 Program Memory Read Cycle Semiconductor Group 52 1997-10-01 C515A t WHLH ALE PSEN t LLDV t LLWL RD t RLRH t RLDV t AVLL t LLAX2 t RLAZ Port 0 A0 - A7 from Ri or DPL Data IN t RHDZ t RHDX A0 - A7 from PCL Instr. IN t AVWL t AVDV Port 2 P2.0 - P2.7 or A8 - A15 from DPH A8 - A15 from PCH MCT00097 Figure 21 Data Memory Read Cycle Semiconductor Group 53 1997-10-01 C515A t WHLH ALE PSEN t LLWL WR t WLWH t QVWX t AVLL t LLAX2 A0 - A7 from Ri or DPL t WHQX t QVWH Data OUT A0 - A7 from PCL Instr.IN Port 0 t AVWL Port 2 P2.0 - P2.7 or A8 - A15 from DPH A8 - A15 from PCH MCT00098 Figure 22 Data Memory Write Cycle t CLCL VCC- 0.5V 0.7 VCC 0.2 VCC- 0.1 0.45V t CHCL t CLCX t CLCH t CHCX MCT00033 Figure 23 External Clock Drive on XTAL2 Semiconductor Group 54 1997-10-01 C515A ROM Verification Characteristics for the C515A-1RM ROM Verification Mode 1 Parameter Address to valid data Symbol min. Limit Values max. 10 tCLCL ns Unit tAVQV - P1.0-P1.7 P2.0-P2.6 Address New Address t AVQV Port 0 Data: Addresses: Data Out P0.0-P0.7 = D0-D7 P1.0-P1.7 = A0-A7 P2.0-P2.6 = A8-A14 Inputs: New Data Out PSEN = V SS ALE, EA = V IH RESET = V IL2 MCS03253 Figure 24 ROM Verification Mode 1 Semiconductor Group 55 1997-10-01 C515A ROM Verification Mode 2 Parameter ALE pulse width ALE period Data valid after ALE Data stable after ALE P3.5 setup to ALE low Oscillator frequency Symbol min. Limit Values typ 2 tCLCL 12 tCLCL - - max. Unit tAWD tACY tDVA tDSA tAS 1/ tCLCL - - - 8 tCLCL - 3.5 - - 4 tCLCL - - 24 ns ns ns ns ns MHz tCLCL - t ACY t AWD ALE t DSA t DVA Port 0 Data Valid t AS P3.5 MCT02613 Figure 25 ROM Verification Mode 2 Semiconductor Group 56 1997-10-01 C515A VCC -0.5 V 0.2 VCC+0.9 Test Points 0.2 VCC -0.1 MCT00039 0.45 V AC Inputs during testing are driven at VCC - 0.5 V for a logic '1' and 0.45 V for a logic '0'. Timing measurements are made at VIHmin for a logic '1' and VILmax for a logic '0'. Figure 26 AC Testing: Input, Output Waveforms VLoad +0.1 V VLoad VLoad -0.1 V Timing Reference Points VOH -0.1 V VOL +0.1 V MCT00038 For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded VOH/VOL level occurs. IOL/IOH 20 mA Figure 27 AC Testing : Float Waveforms Crystal Oscillator Mode C XTAL1 3.5 - 24 MHz XTAL2 C Crystal Mode: C = 20 pF 10 pF (Incl. Stray Capacitance) Driving from External Source N.C. XTAL1 External Oscillator Signal XTAL2 MCS03245 Figure 28 Recommended Oscillator Circuits for Crystal Oscillator Semiconductor Group 57 1997-10-01 C515A Plastic Package, P-MQFP-80-1 (SMD) (Plastic Metric Quad Flat Package) Figure 29 P-MQFP-80-1 Package Outline Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information" SMD = Surface Mounted Device Semiconductor Group 58 Dimensions in mm 1997-10-01 GPM05249 |
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